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XC2C128 CoolRunner-II CPLD
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DS093 (v2.5) October 1, 2004
Preliminary Product Specification
Features
* Optimized for 1.8V systems - As fast as 4.5 ns pin-to-pin delays - As low as 13 A quiescent current Industry's best 0.18 micron CMOS CPLD - Optimized architecture for effective logic synthesis - Multi-voltage I/O operation -- 1.5V to 3.3V Available in multiple package options - 100-pin VQFP with 80 user I/O - 144-pin TQFP with 100 user I/O - 132-ball CP (0.5mm) BGA with 100 user I/O - Pb-free available for all packages Advanced system features - Fastest in system programming * 1.8V ISP using IEEE 1532 (JTAG) interface - IEEE1149.1 JTAG Boundary Scan Test - Optional Schmitt-trigger input (per pin) - Unsurpassed low power management * DataGATE enable (DGE) signal control - Two separate output banks - RealDigital 100% CMOS product term generation - Flexible clocking modes * Optional DualEDGE triggered registers * Clock divider (divide by 2,4,6,8,10,12,14,16) * CoolCLOCK - Global signal options with macrocell control * Multiple global clocks with phase selection per macrocell * Multiple global output enables * Global set/reset - Advanced design security - Open-drain output option for Wired-OR and LED drive - PLA architecture * Superior pinout retention * 100% product term routability across function block - Optional bus-hold, 3-state or weak pull-up on selected I/O pins - Optional configurable grounds on unused I/Os - Mixed I/O voltages compatible with 1.5V, 1.8V, 2.5V, and 3.3V logic levels * SSTL2-1, SSTL3-1, and HSTL-1 I/O compatibility - Hot pluggable
Description
The CoolRunner-II 128-macrocell device is designed for both high performance and low power applications. This lends power savings to high-end communication equipment and high speed to battery operated devices. Due to the low power stand-by and dynamic operation, overall system reliability is improved This device consists of eight Function Blocks inter-connected by a low power Advanced Interconnect Matrix (AIM). The AIM feeds 40 true and complement inputs to each Function Block. The Function Blocks consist of a 40 by 56 P-term PLA and 16 macrocells which contain numerous configuration bits that allow for combinational or registered modes of operation. Additionally, these registers can be globally reset or preset and configured as a D or T flip-flop or as a D latch. There are also multiple clock signals, both global and local product term types, configured on a per macrocell basis. Output pin configurations include slew rate limit, bus hold, pull-up, open drain and programmable grounds. A Schmitt-trigger input is available on a per input pin basis. In addition to storing macrocell output states, the macrocell registers may be configured as direct input registers to store signals directly from input pins. Clocking is available on a global or Function Block basis. Three global clocks are available for all Function Blocks as a synchronous clock source. Macrocell registers can be individually configured to power up to the zero or one state. A global set/reset control line is also available to asynchronously set or reset selected registers during operation. Additional local clock, synchronous clock-enable, asynchronous set/reset and output enable signals can be formed using product terms on a per-macrocell or per-Function Block basis. A DualEDGE flip-flop feature is also available on a per macrocell basis. This feature allows high performance synchronous operation based on lower frequency clocking to help reduce the total power consumption of the device. Circuitry has also been included to divide one externally supplied global clock (GCK2) by eight different selections. This yields divide by even and odd clock frequencies. The use of the clock divide (division by 2) and DualEDGE flip-flop gives the resultant CoolCLOCK feature. DataGATE is a method to selectively disable inputs of the CPLD that are not of interest during certain points in time.
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Refer to the CoolRunnerTM-II family data sheet for architecture description.
(c) 2003 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS093 (v2.5) October 1, 2004 Preliminary Product Specification
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XC2C128 CoolRunner-II CPLD By mapping a signal to the DataGATE function, lower power can be achieved due to reduction in signal switching. Another feature that eases voltage translation is output banking. Two output banks are available on the CoolRunner-II 128 macrocell device that permits easy interfacing to 3.3V, 2.5V, 1.8V, and 1.5V devices. The CoolRunner-II 128 macrocell CPLD is I/O compatible with various JEDEC I/O standards (see Table 1). This device is also 1.5V I/O compatible with the use of Schmitt-trigger inputs.
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Supported I/O Standards
The CoolRunner-II 128 macrocell features LVCMOS, LVTTL, SSTL and HSTL I/O implementations. See Table 1 for I/O standard voltages. The LVTTL I/O standard is a general purpose EIA/JEDEC standard for 3.3V applications that use an LVTTL input buffer and Push-Pull output buffer. The LVCMOS standard is used in 3.3V, 2.5V, 1.8V applications. Both HSTL and SSTL make use of a VREF pin for JEDEC compliance. CoolRunner-II CPLDs are also 1.5V I/O compatible with the use of Schmitt-trigger inputs. Table 1: I/O Standards for XC2C128 Output VCCIO 3.3 3.3 2.5 1.8 1.5 1.5 2.5 3.3 Input VCCIO 3.3 3.3 2.5 1.8 1.5 1.5 2.5 3.3 Board Input Termination VREF Voltage VTT N/A N/A N/A N/A N/A 0.75 1.25 1.5 N/A N/A N/A N/A N/A 0.75 1.25 1.5
RealDigital Design Technology
Xilinx CoolRunner-II CPLDs are fabricated on a 0.18 micron process technology which is derived from leading edge FPGA product development. CoolRunner-II CPLDs employ RealDigital technology, a design technique that makes use of CMOS technology in both the fabrication and design methodology. RealDigital technology employs a cascade of CMOS gates to implement sum of products instead of traditional sense amplifier methodology. Due to this technology, Xilinx CoolRunner-II CPLDs achieve both high-performance and low power operation.
I/O Types LVTTL LVCMOS33 LVCMOS25 LVCMOS18 1.5V I/O HSTL-1 SSTL2-1 SSTL3-1
For information on assigning Vref pins, see XAPP399
80
60
ICC (mA)
40
20
0 0 50 100 150 200 250
DS093_050103
Frequency (MHz)
Figure 1: ICC vs Frequency Table 2: ICC vs Frequency (LVCMOS 1.8V TA = 25C)(1) Frequency (MHz) 0 Typical -4 ICC (mA) Typical -6, -7 ICC (mA) 0.019 3.97 7.95 11.92 15.89 23.83 27.80 31.93 35.73 39.70
Notes: 1. 16-bit up/down, Resetable binary counter (one counter per function block).
25
50
75
100
150
175
200
225
250
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DS093 (v2.5) October 1, 2004 Preliminary Product Specification
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XC2C128 CoolRunner-II CPLD
Absolute Maximum Ratings
Symbol VCC VCCIO VJTAG(2) VAUX VIN(1) VTS(1) TSTG(3) TJ Description Supply voltage relative to ground Supply voltage for output drivers JTAG input voltage limits JTAG input supply voltage Input voltage relative to ground Voltage applied to 3-state output Storage Temperature (ambient) Junction Temperature Value -0.5 to 2.0 -0.5 to 4.0 -0.5 to 4.0 -0.5 to 4.0 -0.5 to 4.0 -0.5 to 4.0 -65 to +150 + 150 Units V V V V V V C C
Notes: 1. Maximum DC undershoot below GND must be limited to either 0.5V or 10 mA, whichever is easiest to achieve. During transitions, the device pins may undershoot to -2.0V or overshoot to +4.5V, provided this over or undershoot lasts less than 10 ns and with the forcing current being limited to 200 mA. 2. Valid over commercial temperature range. 3. For soldering guidelines and thermal considerations, see the Device Packaging information on the Xilinx website. For Pb-free packages, see XAPP427.
Recommended Operating Conditions
Symbol VCC VCCIO Parameter Supply voltage for internal logic and input buffers Commercial TA = 0C to +70C Industrial TA = -40C to +85C Min 1.7 1.7 3.0 2.3 1.7 1.4 1.7 Max 1.9 1.9 3.6 2.7 1.9 1.6 3.6 Units V V V V V V V
Supply voltage for output drivers @ 3.3V operation Supply voltage for output drivers @ 2.5V operation Supply voltage for output drivers @ 1.8V operation Supply voltage for output drivers @ 1.5V operation
VAUX
Supply voltage for JTAG programming
DC Electrical Characteristics (Over Recommended Operating Conditions)
Symbol ICCSB ICCSB ICCSB ICC
(1)
Parameter Standby current (-4) Standby current (-6, -7) Standby current (industrial) Dynamic current (-4) Dynamic current (-6, -7) JTAG input capacitance Global clock input capacitance I/O capacitance Input leakage current I/O High-Z leakage
Test Conditions VCC = 1.9V, VCCIO = 3.6V VCC = 1.9V, VCCIO = 3.6V VCC = 1.9V, VCCIO = 3.6V f = 1 MHz f = 50 MHz f = 1 MHz f = 50 MHz f = 1 MHz f = 1 MHz f = 1 MHz VIN = 0V or VCCIO to 3.9V VIN = 0V or VCCIO to 3.9V
Typical 30 60 -1 -1
Max. 80 150
Units A A A mA mA
ICC (1) CJTAG CCLK CIO IIL(2) IIH
(2)
500 10 10 12 10 1 1
A mA pF pF pF A A
Notes: 1. 16-bit up/down, Resetable binary counter (one counter per function block). 2. See Quality and Reliability section in CoolRunner-II family data sheet for details.
DS093 (v2.5) October 1, 2004 Preliminary Product Specification
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XC2C128 CoolRunner-II CPLD
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LVCMOS and LVTTL 3.3V DC Voltage Specifications
Symbol VCCIO VIH VIL VOH VOL Parameter Input source voltage High level input voltage Low level input voltage High level output voltage Low level output voltage IOH = -8 mA, VCCIO = 3V IOH = -0.1 mA, VCCIO = 3V IOL = 8 mA, VCCIO = 3V IOL = 0.1 mA, VCCIO = 3V Test Conditions Min. 3.0 2.0 -0.3 VCCIO - 0.4V VCCIO - 0.2V Max. 3.6 3.9 0.8 0.4 0.2 Units V V V V V V V
LVCMOS 2.5V DC Voltage Specifications
Symbol VCCIO VIH VIL VOH VOL Parameter Input source voltage High level input voltage Low level input voltage High level output voltage Low level output voltage IOH = -8 mA, VCCIO = 2.3V IOH = -0.1 mA, VCCIO = 2.3V IOL = 8 mA, VCCIO = 2.3V IOL = 0.1 mA, VCCIO = 2.3V Test Conditions Min. 2.3 1.7 -0.3 VCCIO -0.4V VCCIO - 0.2V Max. 2.7 3.9 0.7 0.4 0.2 Units V V V V V V V
LVCMOS 1.8V DC Voltage Specifications
Symbol VCCIO VIH VIL VOH VOL Parameter Input source voltage High level input voltage Low level input voltage High level output voltage Low level output voltage IOH = -8 mA, VCCIO = 1.7V IOH = -0.1 mA, VCCIO = 1.7V IOL = 8 mA, VCCIO = 1.7V IOL = 0.1 mA, VCCIO = 1.7V Test Conditions Min. 1.7 0.65 x VCCIO -0.3 VCCIO - 0.45 VCCIO - 0.2 Max. 1.9 3.9 0.35 x VCCIO 0.45 0.2 Units V V V V V V V
1.5V DC Voltage Specifications(1)
Symbol VCCIO VT+ VTVOH VOL High level output voltage Low level output voltage IOH = -8 mA, VCCIO = 1.4V IOH = -0.1 mA, VCCIO = 1.4V IOL = 8 mA, VCCIO = 1.4V IOL = 0.1 mA, VCCIO = 1.4V
Notes: 1. Hysteresis used on 1.5V inputs.
Parameter Input source voltage Input hysteresis threshold voltage
Test Conditions
Min. 1.4 0.5 x VCCIO 0.2 x VCCIO VCCIO - 0.45 VCCIO - 0.2
Max. 1.6 0.8 x VCCIO 0.5 x VCCIO
Units V V V V V
0.4 0.2
V V
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DS093 (v2.5) October 1, 2004 Preliminary Product Specification
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XC2C128 CoolRunner-II CPLD
Schmitt Trigger Input DC Voltage Specifications
Symbol VCCIO VT+ VTParameter Input source voltage Input hysteresis threshold voltage Test Conditions Min. 1.4 0.5 x VCCIO 0.2 x VCCIO Max. 3.9 0.8 x VCCIO 0.5 x VCCIO Units V V V
SSTL2-1 DC Voltage Specifications
Symbol VCCIO VREF(1) VTT VIH VIL VOH VOL
(2)
Parameter Input source voltage Input reference voltage Termination voltage High level input voltage Low level input voltage High level output voltage Low level output voltage
Test Conditions
Min. 2.3 1.15 VREF - 0.04 VREF + 0.18 -0.3
Typ. 2.5 1.25 1.25 -
Max. 2.7 1.35 VREF + 0.04 3.9 VREF - 0.18 0.54
Units V V V V V V V
IOH = -8 mA, VCCIO = 2.3V IOL = 8 mA, VCCIO = 2.3V
VCCIO - 0.62 -
Notes: 1. VREF should track the variations in VCCIO, also peak to peak ac noise on VREF may not exceed 2% VREF. 2. VTT of transmitting device must track VREF of receiving devices.
SSTL3-1 DC Voltage Specifications
Symbol VCCIO VREF(1) VTT(2) VIH VIL VOH VOL Parameter Input source voltage Input reference voltage Termination voltage High level input voltage Low level input voltage High level output voltage Low level output voltage IOH = -8 mA, VCCIO = 3V IOL = 8 mA, VCCIO = 3V Test Conditions Min. 3.0 1.3 VREF - 0.05 VREF + 0.2 -0.3 VCCIO - 1.1 Typ. 3.3 1.5 1.5 Max. 3.6 1.7 VREF + 0.05 VCCIO + 0.3 VREF - 0.2 0.7 Units V V V V V V V
Notes: 1. VREF should track the variations in VCCIO, also peak to peak ac noise on VREF may not exceed 2% VREF. 2. VTT of transmitting device must track VREF of receiving devices.
HSTL1 DC Voltage Specifications
Symbol VCCIO VREF(1) VTT(2) VIH VIL VOH VOL Parameter Input source voltage Input reference voltage Termination voltage High level input voltage Low level input voltage High level output voltage Low level output voltage IOH = -8 mA, VCCIO = 1.7V IOL = 8 mA, VCCIO = 1.7V VREF + 0.1 -0.3 VCCIO -0.4 Test Conditions Min. 1.4 0.68 Typ. 1.5 0.75 VCCIO x 0.5 1.9 VREF - 0.1 0.4 Max. 1.6 0.90 Units V V V V V V V
Notes: 1. VREF should track the variations in VCCIO, also peak to peak ac noise on VREF may not exceed 2% VREF. 2. VTT of transmitting device must track VREF of receiving devices.
DS093 (v2.5) October 1, 2004 Preliminary Product Specification
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XC2C128 CoolRunner-II CPLD
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AC Electrical Characteristics Over Recommended Operating Conditions
-4(5) Symbol TPD1 TPD2 TSUD TSU1 TSU2 THD TH TCO FTOGGLE
(1) (2) (2)
-6 Min. 3.2 2.4 2.7 0.0 0.0 2.1 1.3 1.6 0.2 0.7 2.5 0.0 1.1 6.0 6.0 0.0 4.0 3.0 1.3 0.0 Max. 5.7 6.0 4.2 450 270 250 152 145 5.3 5.6 6.4 7.2 6.0 5.0 8.2 350 Min. 4.0 2.8 3.3 0.0 0.0 2.7 1.5 2.0 0.2 1.0 3.1 0.0 1.6 7.5 7.5 0.0 6.0 4.0 2.0 0.0 -
-7 Max . 7.0 7.5 6.0 300 152 141 114 108 7.3 7.0 8.0 9.9 8.1 7.6 9.0 350 Unit s ns ns ns ns ns ns ns ns MHz MHz MHz MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns us
Parameter Propagation delay single p-term Propagation delay OR array Direct input register set-up time Setup time fast (single p-term) Setup time (OR array) Direct input register hold time Hold time (Or array or p-term) Clock to output Internal toggle rate Maximum system frequency Maximum system frequency Maximum external frequency Maximum external frequency Direct input register p-term clock setup time P-term clock setup time (single p-term) P-term clock setup time (OR array) Direct input register p-term clock hold time P-term clock hold P-term clock to output Global OE to output enable/disable P-term OE to output enable/disable Macrocell driven OE to output enable/disable P-term set/reset to output valid Global set/reset to output valid Register clock enable setup time Register clock enable hold time Global clock pulse width High or Low Asynchronous preset/reset pulse width (High or Low) P-term pulse width High or Low Set-up before DataGATE latch assertion Hold to DataGATE latch assertion DataGATE recovery to new data DataGATE low pulse width CDRST setup time before falling edge GCLK2 Hold time CDRST after falling edge GCLK2 Configuration time
Min. 2.3 1.8 2.1 0.0 0.0 1.6 1.1 1.4 0.0 0.3 1.9 0.0 0.9 4.5 4.5 0.0 5.0 2.0 0.8 0.0 -
Max. 4.2 4.5 3.4 500 333 303 192 182 4.1 4.3 4.8 5.5 4.9 4.4 5.0 350
FSYSTEM1 FSYSTEM2 FEXT1(3) FEXT2(3) TPSUD TPSU1 TPSU2 TPHD TPH TPCO TOE/TOD
TPOE/TPOD TMOE/TMOD TPAO TAO TSUEC THEC TCW TAPRPW TPCW TDGSU TDGH TDGR TDGW TCDRSU TCDRH TCONFIG(4)
Notes: 1. FTOGGLE is the maximum clock frequency to which a T flip-flop can reliably toggle (see the CoolRunner-II family data sheet). 2. FSYSTEM1 is the internal operating frequency for a device with 16-bit resetable binary counter through one p-term per macrocell while FSYSTEM2 is through the OR array (one counter per function block). 3. FEXT1 (1/TSU1+TCO) is the maximum external frequency using one p-term while FEXT2 is through the OR array. 4. Typical configuration current during TCONFIG is 10 mA. 5. The -4 speed grade is Advance Specification.
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DS093 (v2.5) October 1, 2004 Preliminary Product Specification
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XC2C128 CoolRunner-II CPLD
Internal Timing Parameters
-4(2) Symbol Buffer Delays TIN Input buffer delay TDIN TGCK TGSR TGTS TOUT Parameter(1) Min. 1.2 0.0 1.2 0.0 Max. 1.6 2.5 1.4 1.5 1.6 1.8 2.7 0.5 0.4 0.3 0.4 1.2 0.2 1.0 0.0 1.2 1.2 2.0 0.5 2.0 2.0 0.0 2.0 Min. 1.4 0.0 1.4 0.0 -6 Max. 2.0 3.3 1.5 1.6 1.8 2.3 3.8 0.6 0.5 0.3 0.9 2.1 0.4 1.1 0.0 1.4 1.5 3.0 0.8 4.0 2.0 0.0 2.0 Min. 1.8 0.0 1.8 0.0 -7 Max. 2.6 4.9 2.7 3.5 3.0 2.6 4.0 1.4 1.1 0.5 0.7 2.5 0.7 1.5 0.0 3.0 2.0 4.0 1.0 4.0 4.0 0.0 4.0 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Direct data register input delay Global Clock buffer delay Global set/reset buffer delay Global 3-state buffer delay Output buffer delay
TEN Output buffer enable/disable delay P-term Delays TCT Control term delay TLOGI1 Single P-term delay adder TLOGI2 Multiple P-term delay adder Macrocell Delay TPDI Input to output valid TLDI TSUI THI TECSU TECHO TCOI TAOI Setup before clock (transparent latch) Setup before clock Hold after clock Enable clock setup time Enable clock hold time Clock to output valid Set/reset to output valid
TCDBL Clock doubler delay Feedback Delays TF Feedback delay TOEM Macrocell to global OE delay I/O Standard Time Adder Delays 1.5V I/O THYS15 Hysteresis input adder TOUT15 Output adder TSLEW15 Output slew rate adder I/O Standard Time Adder Delays 1.8V CMOS THYS18 Hysteresis input adder TOUT18 TSLEW Output adder Output slew rate adder
DS093 (v2.5) October 1, 2004 Preliminary Product Specification
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XC2C128 CoolRunner-II CPLD
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Internal Timing Parameters (Continued)
-4(2) Symbol TIN25 THYS25 TOUT25 Parameter(1) Standard input adder Hysteresis input adder Output adder Min. Max. 0.5 1.5 0.7 2.0 0.4 1.0 1.0 2.0 0.3 -0.5 0.3 -0.5 0.5 0.0 Min. I/O Standard Time Adder Delays 2.5V CMOS
-6 Max. 0.6 1.5 0.8 3.0 0.5 1.2 1.2 3.0 0.4 -0.5 0.4 -0.5 0.6 0.0 Min. -
-7 Max. 1.0 3.0 3.0 4.0 2.0 3.0 3.0 4.0 2.5 0.0 2.5 0.0 2.5 0.0 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns
TSLEW25 Output slew rate adder I/O Standard Time Adder Delays 3.3V CMOS/TTL TIN33 Standard input adder THYS33 TOUT33 Hysteresis input adder Output adder
TSLEW33 Output slew rate adder I/O Standard Time Adder Delays HSTL, SSTL SSTL2-1 Input adder to TIN, TDIN, TGCK, TGSR, TGTS Output adder to TOUT SSTL3-1 Input adder to TIN, TDIN, TGCK, TGSR, TGTS Output adder to TOUT HSTL-1 Input adder to TIN, TDIN, TGCK, TGSR, TGTS Output adder to TOUT
Notes: 1. 1.5 ns input pin signal rise/fall. 2. The -4 speed grade is Advance Specification.
Switching Characteristics
VCC = VCCIO = 1.8V, 25oC
5.0
Switching Test Conditions
4.8
4.6
TPD2 (ns)
4.4
4.2
4.0 1 2 4 8 16
Figure 3: AC Load Circuits
Number of Outputs Switching
DS093_02_050103
Figure 2: Derating Curve for TPD
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DS093 (v2.5) October 1, 2004 Preliminary Product Specification
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XC2C128 CoolRunner-II CPLD
Typical I/V Output Curves
3.3V
60
50
IO (Output Current mA)
40 1.8V 30
2.5V
Iol
20 1.5V 10
0 0 .5 1.0 1.5 2.0 2.5 3.0 3.5
VO (Output Volts)
XC128_IV_all_050703
Figure 4: Typical I/V Curves for XC2C128
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Pin Descriptions
Function Block 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1(GTS1) 1(GTS0) Macrocell 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 VQ100 CP132 TQ144 13 12 11 10 9 8 7 6 4 3 G1 F1 F2 F3 E1 E2 E3 D1 D2 C1 C2 C3 17 16 15 14 13 12 11 10 9 7 6 5 I/O Bank 2 2 2 2 2 2 2 2 2 2 2 2
Pin Descriptions (Continued)
Function Block 2 2 2 2 2 2 2 2 2 2 2 2 2(GCK0) 2(GCK1) 2(CDRST) 2(GCK2) Macrocell 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 VQ100 CP132 TQ144 14 15 16 17 18 19 22 23 24 27 G2 G3 H1 H2 H3 J1 J2 K1 K3 L2 M2 N2 19 21 22 23 24 25 26 28 30 32 35 38 I/O Bank 1 1 1 1 1 1 1 1 1 1 1 1
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XC2C128 CoolRunner-II CPLD
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Pin Descriptions (Continued)
Function Block 3 3(GTS3) 3(GTS2) 3(GSR) 3 3 3 3 3 3 3 3 3 3 3 3 4(DGE) 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 Macrocell 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 93 92 91 90 28 29 30 32 33 34 35 36 37 39 40 VQ100 CP132 TQ144 2 1 99 97 96 95 94 B1 B2 A1 A3 B4 A4 C5 B5 A5 C6 B6 A6 C7 P2 M3 N3 P3 M4 M5 N5 P5 M6 N6 P6 N7 M7 4 3 2 143 140 138 136 134 133 132 131 130 129 39 40 41 43 45 49 50 51 52 53 54 56 57 I/O Bank 2 2 2 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1
Pin Descriptions (Continued)
Function Block 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 Macrocell 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 VQ100 CP132 TQ144 65 66 67 68 70 71 72 73 74 76 64 63 61 60 59 58 56 55 54 G13 G12 F14 F13 F12 E13 E12 D14 D13 D12 C14 B13 A13 H12 H13 J13 J12 K14 K13 L14 L13 L12 M14 M13 M12 94 95 96 97 98 100 101 102 103 104 105 110 111 92 91 88 87 86 85 83 82 81 80 79 78 I/O Bank 2 2 2 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1
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DS093 (v2.5) October 1, 2004 Preliminary Product Specification
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XC2C128 CoolRunner-II CPLD
Pin Descriptions (Continued)
Function Block 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 Macrocell 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 VQ100 CP132 TQ144 77 78 79 80 81 82 85 86 87 89 C12 B12 A12 C11 B11 A11 C10 A10 C9 A8 B8 C8 B7 112 113 115 116 117 118 119 120 121 124 125 126 128 I/O Bank 2 2 2 2 2 2 2 2 2 2 2 2 2
Pin Descriptions (Continued)
Function Block 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Macrocell 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 VQ100 CP132 TQ144 53 52 50 49 46 44 43 42 41 N14 N13 P14 P12 M11 N11 P11 P10 P9 M8 N8 P8 77 76 74 71 70 69 68 64 61 60 59 58 I/O Bank 1 1 1 1 1 1 1 1 1 1 1 1
Notes: 1. GTS = global output enable, GSR = global reset/set, GCK = global clock, CDRST = clock divide reset, DGE = DataGATE enable.
XC2C128 JTAG, Power/Ground, No Connect Pins and Total User I/O
Pin Type TCK TDI TDO TMS VAUX (JTAG supply voltage) Power internal (VCC) Power Bank 1 I/O (VCCIO1) Power Bank 2 I/O (VCCIO2) Ground No connects VQ100(1) 48 45 83 47 5 26, 57 20, 38, 51 88, 98 21, 25, 31, 62, 69, 75, 84, 100 CP132(1) M10 M9 B9 N10 D3 P1, K12, A2 J3, P7, G14, P13 A14, C4, A7 K2, N1, P4, N9, N12, J14, H14, E14, B14, A9, B3 L1, L3, M1, N4, C13, B10 TQ144(1) 67 63 122 65 8 1, 37, 84 27, 55, 73, 93 109, 127, 141 29, 36, 47, 62, 72, 89, 90, 99, 108, 123, 144 18, 20, 31, 33, 34, 42, 44, 46, 48, 66, 75, 106, 107, 114, 135, 137, 139, 142 100
Total user I/O (including dual function pins)
80
100
Notes: 1. Pin compatible with all larger and smaller densities except where I/O banking is used.
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XC2C128 CoolRunner-II CPLD
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Ordering Information
Part Number XC2C128-4VQ100C(2) XC2C128-6VQ100C XC2C128-7VQ100C XC2C128-4CP132C(2) XC2C128-6CP132C XC2C128-7CP132C XC2C128-4TQ144C(2) XC2C128-6TQ144C XC2C128-7TQ144C XC2C128-4VQG100C(2) XC2C128-6VQG100C XC2C128-7VQG100C XC2C128-4CPG132C(2) XC2C128-6CPG132C XC2C128-7CPG132C XC2C128-4TQG144C(2) XC2C128-6TQG144C XC2C128-7TQG144C XC2C128-7VQ100I XC2C128-7CP132I XC2C128-7TQ144I XC2C128-7VQG100I Pin/Ball Spacing 0.5mm 0.5mm 0.5mm 0.5mm 0.5mm 0.5mm 0.5mm 0.5mm 0.5mm 0.5mm 0.5mm 0.5mm 0.5mm 0.5mm 0.5mm 0.5mm 0.5mm 0.5mm 0.5mm 0.5mm 0.5mm 0.5mm JA (C/Watt) 47.5 47.5 47.5 72.4 72.4 72.4 46.1 46.1 46.1 47.5 47.5 47.5 72.4 72.4 72.4 46.1 46.1 46.1 47.5 72.4 46.1 47.5 JC (C/Watt) 12.5 12.5 12.5 15.7 15.7 15.7 7.9 7.9 7.9 12.5 12.5 12.5 15.7 15.7 15.7 7.9 7.9 7.9 12.5 15.7 7.9 12.5 Package Type Very Thin Quad Flat Pack Very Thin Quad Flat Pack Very Thin Quad Flat Pack Chip Scale Package Chip Scale Package Chip Scale Package Thin Quad Flat Pack Thin Quad Flat Pack Thin Quad Flat Pack Very Thin Quad Flat Pack; Pb-free Very Thin Quad Flat Pack; Pb-free Very Thin Quad Flat Pack; Pb-free Chip Scale Package; Pb-free Chip Scale Package; Pb-free Chip Scale Package; Pb-free Thin Quad Flat Pack; Pb-free Thin Quad Flat Pack; Pb-free Thin Quad Flat Pack; Pb-free Very Thin Quad Flat Pack Chip Scale Package Thin Quad Flat Pack Very Thin Quad Flat Pack; Pb-free Package Body Dimensions 14mm x 14mm 14mm x 14mm 14mm x 14mm 8mm x 8mm 8mm x 8mm 8mm x 8mm 20mm x 20mm 20mm x 20mm 20mm x 20mm 14mm x 14mm 14mm x 14mm 14mm x 14mm 8mm x 8mm 8mm x 8mm 8mm x 8mm 20mm x 20mm 20mm x 20mm 20mm x 20mm 14mm x 14mm 8mm x 8mm 20mm x 20mm 14mm x 14mm Comm. (C) I/O 80 80 80 100 100 100 100 100 100 80 80 80 100 100 100 100 100 100 80 100 100 80 Ind. (I)(1) C C C C C C C C C C C C C C C C C C I I I I
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DS093 (v2.5) October 1, 2004 Preliminary Product Specification
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XC2C128 CoolRunner-II CPLD
Part Number XC2C128-7CPG132I XC2C128-7TQG144I
Pin/Ball Spacing 0.5mm 0.5mm
JA (C/Watt) 72.4 46.1
JC (C/Watt) 15.7 7.9
Package Type Chip Scale Package; Pb-free Thin Quad Flat Pack; Pb-free
Package Body Dimensions 8mm x 8mm 20mm x 20mm
Comm. (C) I/O 100 100 Ind. (I)(1) I I
Notes: 1. C = Commercial (T A = 0 C to +70 C); I = Industrial (T A = -40 C to +85 C) 2. Inquire with your local sales representative for availability of this part.
Standard Example: XC2C128 Device Speed Grade Package Type Number of Pins Temperature Range
-4 TQ
144
C
Pb-Free Example: XC2C128 Device Speed Grade Package Type Pb-Free Number of Pins Temperature Range
-4 TQ
G
144
C
Device Part Marking
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Device Type Package Speed Operating Range
XC2Cxxx TQ144 7C
This line not related to device part number
Part Marking for all non chip scale packages
Figure 5: Sample Package with Part Marking Note: Due to the small size of chip scale packages, the complete ordering part number cannot be included on the package marking. Part marking on chip scale packages by line are: * * * Line 1 = X (Xilinx logo) then truncated part number Line 2 = Not related to device part number Line 3 = Not related to device part number * Line 4 = Package code, speed, operating temperature, three digits not related to device part number. Package codes: C5 = CP132, C6 = CPG132.
DS093 (v2.5) October 1, 2004 Preliminary Product Specification
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XC2C128 CoolRunner-II CPLD
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VCC I/O(2) I/O(5) I/O I/O GND I/O I/O I/O I/O I/O I/O VCCIO1 I/O I/O I/O I/O I/O I/O TDI I/O TMS TCK I/O I/O
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
I/O(1) I/O(1) I/O(1) I/O(1) VAUX I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCIO1 GND I/O(2) I/O(2) I/O(4) GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
VCCIO2
I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCIO2 I/O I/O I/O GND TDO I/O I/O I/O I/O I/O I/O I/O
GND I/O(3)
VQ100 Top View
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
GND I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O VCC I/O I/O I/O I/O I/O VCCIO1
(1) (2) (3) (4) (5)
-
Global Output Enable Global Clock Global Set/Reset Clock Divide Reset Data Gate
Figure 6: VQ100 Very Thin Quad Flat Pack
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DS093 (v2.5) October 1, 2004 Preliminary Product Specification
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XC2C128 CoolRunner-II CPLD
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11
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VCCIO1 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O NC I/O I/O
P N M L K J H G F E D C B A
VCC GND
I/O(5) I/O(2)
I/O I/O
GND NC
I/O I/O
I/O I/O
VCCIO1 I/O
I/O I/O
I/O GND
I/O TMS
I/O I/O
I/O GND
I/O I/O
NC
I/O(4)
I/O
I/O
I/O
I/O
I/O
I/O
TDI
TCK
I/O
I/O
I/O
NC
I/O(2)
NC
I/O
I/O
I/O
GND
I/O(2)
VCC
I/O
I/O
I/O
VCCIO1
I/O
GND
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
CP132 Bottom View
I/O
VCCIO1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
VAUX
I/O
I/O
I/O
I/O(1)
I/O(1)
VCCIO2
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O I/O(1)
I/O(1) VCC
GND I/O(3)
I/O I/O
I/O I/O
I/O I/O
I/O VCCIO2
I/O I/O
TDO GND
NC I/O
I/O I/O
I/O I/O
GND VCCIO2
(1) - Global Output Enable (2) - Global Clock (3) - Global Set/Reset (4) - Clock Divide Reset (5) - DataGATE Enable
Figure 7: CP132 Chip Scale Package
DS093 (v2.5) October 1, 2004 Preliminary Product Specification
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1
2
3
4
5
6
7
8
9
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XC2C128 CoolRunner-II CPLD
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VCC I/O(1) I/O(1) I/O I/O(1) I/O(1) I/O VAUX I/O I/O I/O I/O I/O I/O I/O I/O I/O NC I/O NC I/O I/O I/O I/O I/O I/O VCCIO1 I/O GND I/O(2) NC I/O(2) NC NC I/O(4) GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109
GND I/O(3) NC VCCIO2 I/O NC I/O NC I/O NC I/O I/O I/O I/O I/O I/O I/O VCCIO2 I/O I/O I/O GND TDO I/O I/O I/O I/O I/O I/O I/O NC I/O I/O I/O I/O VCCIO2
TQ144 Top View
108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73
GND NC NC I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O VCCIO1 I/O I/O GND GND I/O I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O I/O I/O NC I/O VCCIO1
VCC I/O(2) I/O(5) I/O I/O NC I/O NC I/O NC GND NC I/O I/O I/O I/O I/O I/O
Figure 8: TQ144 Thin Quad Flat Pack
Additional Information
CoolRunner-II Datasheets and Application Notes Device Packages
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VCCIO1 I/O I/O I/O I/O I/O I/O GND TDI I/O TMS NC TCK I/O I/O I/O I/O GND
37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
(1) - Global Output Enable (2) - Global Clock (3) - Global Set/Reset (4) - Clock Divide Reset (5) - DataGATE Enable
DS093 (v2.5) October 1, 2004 Preliminary Product Specification
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XC2C128 CoolRunner-II CPLD
Revision History
The following table shows the revision history for this document. Date 10/01/02 5/19/03 8/25/03 01/26/04 03/01/04 7/30/04 10/01/04 Version 1.0 2.0 2.1 2.2 2.3 2.4 2.5 Initial Xilinx release. Added bin 6, 7 characterization data. Edit Package diagram, other minor formating edits. Update links. Fixed cropping on Figure 6. Added Pb-free documentation. Add Asynchronous Preset/Reset Pulse Width specification to AC Electrical Characteristics. Revision
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